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Why it's important

Slip in phase and frequency is detrimental to normal operation in mobile TDD
(Time Division Duplex) band causing inter-cell interference and eventually effecting call degradation
and hand-off coordination

PtP

PTP leverages hardware time stamping of PTP PDUs to achieve
sub-100 nanosecond level accuracy while
filtering dynamic time error accumulation along the way

The version 2 of IEEE 1588

introduces the concept of “profile”

G.8265.1

ITU-T G.8265.1 telecom profile is specified for frequency synchronization

>>> G.8275.1 Full Timing Support (FTS)

G.8265.2

ITU-T G.8275.1/G.8275.2 are for phase/time synchronization

>>> G.8275.2 Partial timing support (PTS)

>>> G.8275.2 Assisted Partial timing support (APTS)

>>> E2E Transparent Clock , PTP Master

Diagram

PtP config

Attached to GM clock on ce44

Code Block

title	SyncE Config
collapse	true

show runn ptp
!
ptp clock 0 profile g8275.1
 number-ports 5
 system-clock-sync 30
 clock-port 1
  network-interface ce44
  exit
 clock-port 2
  master-only
  network-interface ce1
  exit
 clock-port 4
  master-only
  network-interface ce3
  exit

uk-wnlb-lg-pol-cin-01(config-clk-port)#2024 Jul 19 11:03:11.566 : uk-wnlb-lg-pol-cin-01 : HSL : CRITI : [PTP_SERVO_STATE_2]: Phase Locked. -> Holdover in Spec.

Code Block

title	show ptp servo

uk-wnlb-lg-pol-cin-01#show ptp servo
PTP servo status for clock 0
  Servo Config                : Freq + Phase Correction
  Servo State                 : Holdover-in-spec
  Servo State Duration        : 00:03:51
  Servo APTS Mode             : N/A
  Frequency Correction        : 0.000 ppb
  Phase Correction            : 977250000.000 nsec
  Offset From Master          : 0 nsec
  Mean Path Delay             : 13 nsec
  APTS GPS to PTP Offset      : N/A
  Sync Packet Rate            : 16
  Delay Packet Rate           : 16

Code Block

title	show ptp clock 0

Versions Compared

Old Version 8

New Version 9

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